1. Field of the Invention
This invention is related to a method which employs side wall processing during the manufacture of a semiconductor device.
2. Description of the Related Art
Semiconductor devices are now widely used in a number of different fields. The demands for small scale semiconductor devices, reductions in the amount of energy consumption, improvements in reliability, and reductions in costs are increasing year by year. Particularly, in order to achieve small scale semiconductor devices an increased level of manufacturing technology is being demanded as the number of elements included in a semiconductor device per unit area is increasing.
A reduction in wiring width or a reduction in spaces between wirings is given as one method for achieving small scale semiconductor devices. However, in contemporary lithography technologies in which a pattern such as a wiring is formed using optical lithography, there are limits to the level of resolution due to the wavelength used. Thus, as a method which overcomes the limits of this resolution for forming a pattern, the side wall processing (also called side wall transfer processing) is proposed, for example, in Japan Patent Laid Open Heisei 8-55908.
The side wall processing comprises the following steps: 1) A sacrificial layer is formed on a layer to be processed; 2) The sacrificial layer is patterned by lithography, for example. The sacrificial layer may be processed by slimming; 3) at or beside the side wall of the sacrificial layer another sacrificial layer is formed as a mask; 4) using this sacrificial layer as a mask the layer to be processed is etched. By the side wall processing, it is possible to form a detailed pattern which exceeds the resolution limits of lithography when the side wall processing is used.
However, in the side wall processing there are constraints to the shape of a pattern which is formed by a sacrificial layer used as a mask. As a result, the pattern which can be obtained by etching a layer to be processed includes unnecessary wiring patterns and short circuits are sometimes generated via these unnecessary wirings. In addition, when a pattern density formed by a sacrificial layer which becomes a mask changes significantly depending on the positions, the microloading effect sometimes occurs. This is because the speed of etching the layer to be processed changes depending on the positions. Also, the dishing effect sometimes occurs during a CMP (Chemical Mechanical Polishing) process in a damascene process which is performed after the layer to be processed is etched. As a result, it becomes difficult to improve the yield.